July 24th, 2017 by Adam Armstrong
WDC Announces Four-Bits-Per-Cell 3D NAND Technology
Today Western Digital Corp. announced that it has successfully developed four bits per cell, X4, flash memory architecture offering on 64-layer 3D NAND, BiCS3, technology. WD has taken its innovation of X4 technology on its 2D NAND, built off of that (both form a technological and commercial aspect) and developed the new X4 technology for 3D NAND. WD will be showcasing new SSDs with the BiCS3 X4 technology in August at the Flash Memory Summit in Santa Clara, California.
Western Digital has a long track record of industry firsts surrounding flash technology, going back nearly 30 years. These first include multi-level cell (MLC) flash technologies using two bits (X2) and three bits (X3) per cell. Utilizing the company’s deep vertical integration capabilities (including silicon wafer processing, device engineering to provide sixteen distinct data levels in every storage node, and system expertise for overall flash management) the company was able to bring this new X4 technology to market. The new BiCS3 X4 technology is stated to deliver storage capacity of 768 gigabits on a single chip, a 50% increase from the prior 512 gigabit chip that was enabled with the three bits per cell (X3) architecture. This increase in capacity will still be able to deliver performance comparable to the BiCS3 X3 technology, according to WD.
The 3D NAND X4 Technology will most likely be leveraged in several of WD product lines, increasing capacity as it is integrated. WD also intends to add the X4 technology to future generations of its 3D NAND technology, including the 96-layer BiCS4.