NVIDIA has added CUDA-Q Logical to its open-source CUDA-Q platform, an orchestration layer for building applications that run on fault-tolerant quantum computers, and it arrives with two numbers that are interesting. Fermilab says the tool cut a fault-tolerant algorithm design cycle from five months to three weeks, and Iceberg Quantum used it to show that Diraq’s spin-qubit hardware can reach 1,000 logical qubits with 150,000 physical qubits, roughly 10x fewer than Diraq’s previous estimate. Both results are early-access work reported by the labs and vendors involved, but they’re the first concrete figures for a tool aimed at the next stage of quantum computing, where error-corrected logical qubits replace raw physical ones.
Why Codesign Is the Bottleneck
Fault-tolerant processors built on logical qubits are what make useful quantum computing possible, because they overcome the errors inherent in physical qubits and can execute the larger computations that drug discovery, financial modeling, and materials science need. Designing an application for one of those systems means juggling the algorithm, the error-correction code, the hardware architecture, and the rest of the QPU at the same time, and NVIDIA says that changing any one of them can swing the resources the application needs. CUDA-Q Logical lets researchers describe all of those components together and swap between options to find the configuration that performs best with logical qubits.
“Quantum computing is maturing into an era of logical qubits, and researchers need an open, customizable platform capable of representing all aspects of a fault-tolerant system,” said Timothy Costa, vice president and general manager of quantum at NVIDIA. NVIDIA lists Fermi National Accelerator Laboratory, Infleqtion, IQM Quantum Computers, QCDesign, Quantum Motion, and Sandia National Laboratories among the QPU makers and labs already using it.
Iceberg Maps Its qLDPC Architecture Onto Diraq’s Spin Qubits
The headline result comes from Iceberg Quantum, which used CUDA-Q Logical to model its Pinnacle error-correction architecture on Diraq’s silicon spin-qubit hardware. Pinnacle is a quantum low-density parity-check (qLDPC) code, a family that promises far lower overhead than the surface code but is usually assumed to demand more complex hardware. Diraq’s write-up says the modeling showed Pinnacle can run on its hardware without asking much more of the platform than a surface-code approach would, with non-local connectivity confined to modular processing blocks and qubit shuttling schedules tuned so shuttling contributes no more to the error budget than physical gates. The hardware-aware physical qubit counts landed within 5% of the figures in the original Pinnacle paper, which is how the two companies arrive at 1,000 logical qubits from 150,000 physical ones, the figure Diraq now reports in its “The Case for Silicon” white paper and roughly 10x below its earlier estimate. Diraq CEO Andrew Dzurak called it an order-of-magnitude increase in the projected logical performance of each device.
Fermilab Cuts Development Time From Five Months to Three Weeks
Fermilab used CUDA-Q Logical in early work to validate prior results and evaluate physical qubit requirements, runtimes, and other resources across different error-correction approaches and hardware. The lab says that turned fault-tolerant system design into a repeatable, verifiable computational workflow and compressed algorithm development from five months to three weeks, a 7x speedup. “Using CUDA-Q Logical, our team explored combinations of these resources in just three weeks, compared with what would have typically taken about five months of building specialized infrastructure,” said Anna Grassellino, chief technology officer at Fermilab and director of the Superconducting Quantum Materials and Systems Center.
Sandia’s QUOPS Benchmark Ships in CUDA-Q
Alongside the orchestration layer, NVIDIA is shipping a reference implementation of QUOPS, a cross-platform, hardware-agnostic benchmark from Sandia National Laboratories that measures progress toward utility-scale, fault-tolerant quantum computing. The field has mostly tracked itself through physical-qubit metrics such as qubit count, gate fidelity, and coherence time; QUOPS is meant to score how close a system is to running useful workloads. Sandia posted a preprint ahead of IEEE Quantum Week with initial QUOPS results for QPUs from Google, IBM, and Quantinuum. “We created QUOPS to do exactly that, and we’re excited to see it used by quantum computing vendors and customers,” said Timothy Proctor, co-director of Sandia’s Quantum Performance Laboratory, referring to the need to track and forecast the growth of quantum computer capabilities.
The Rest of the Quantum-GPU Stack
The same announcement rounds up adoption across NVIDIA’s quantum lineup. Diraq used NVIDIA Ising, which NVIDIA calls the first family of open models for building and deploying AI for useful quantum computing, to calibrate its silicon qubit processor. Anyon Computing, Quandela, and Quantum Machines each built on NVQLink, NVIDIA’s open architecture for coupling QPUs to GPU supercomputers, with Quantum Machines running an integration demo at the Israeli Quantum Computing Center. IonQ reported progress on DQAOA-GPT, a quantum generative AI framework; MITRE published work on GPU-accelerated digital twins of quantum sensors; Phasecraft is using cuQuantum to build what it describes as the largest emulated molecular database generated by a variational quantum eigensolver, and UCLA and Caltech are working on the control sequences needed to run quantum applications.
The timing puts NVIDIA’s software layer in the same conversation as the hardware roadmaps we’ve been tracking, including IBM’s path to a fault-tolerant machine in 2029 e 120-qubit Nighthawk r2 headed to CSCS. CUDA-Q Logical is available now on GitHub, and the QUOPS reference implementation ships in CUDA-Q, with Sandia’s benchmark repository published separately.
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