SSD Flash

Solid State Flash memory is available using NAND and NOR technology. NOR technology allows direct random addressing and data flow in the same way that a normal RAM memory chip does, permitting it to be used for program storage and execution within a processing system. NOR Flash chips are slower, less dense, and have a limited rewrite endurance capability making them inferior to NAND based solutions when used as an alternative to a rotating disk.

NAND Flash technology is a serial memory just like a disk drive. Data is addressed and stored in blocks rather than as individual addressable bits or bytes. NAND Flash based Solid State Drives are designed to mimic a rotating magnetic disk from the system perspective, offering faster access time and comparable data throughput rates. The main disadvantage of a SSD relative to magnetic disk is data density and cost per megabyte.

For sake of this section, we will focus on NAND components as they dominate SSD offerings. NAND Flash components come in densities from 1Gb (gigabit) to 64Gb per chip. There are also Single Level Cell (SLC) and Multi-Level Cell (MLC) configurations, with SLC able to store a single bit per cell and MLC able to store more than 1 bit per cell.

Similar to sectors and tracks on a magnetic drive, NAND Flash components have structures called pages and blocks. Pages are sectors and blocks are analogous to tracks, and, just like on a disk, there is an Error Correction Code (ECC) associated with each sector. A common NAND Flash component configuration is 128 pages of 4,096+128 bytes each for a block size of 512 KB. Data is read and written sequentially, also just like a disk.

NAND Flash also has inherent cell defects, much like surface defects on a disk. Because of this, spare data blocks are provided in the device and a remapping table is provided in the device to allow system software to mask out faulty data blocks as they are discovered.

Unlike a magnetic disk, NAND Flash has a limited rewrite endurance of about 1,000,000 times per block. You just can’t write to the same blocks indefinitely. Because of this, a wear-leveling scheme is used to move more commonly accessed areas, such as a directory, periodically. Wear-leveling is similar to defragging a hard disk however in the case of NAND Flash, it needs to happen or else data may eventually be lost.

Some support for wear-leveling is built in to some Flash chips, though this function is mostly performed by the controller or system software layer. A lot of effort is made to hide the wear-leveling activity so that it does not interfere with normal device performance.

The Open NAND Flash Interface group (ONFI) developed a Standard for NAND Flash components that has been widely adopted by the industry. This standard provides a common I/O and command set, and effectively standardized a common architecture for ONFI compliant components. This architecture includes the following common elements:

Data Interface – usually 8 bit, sometimes 16 bit in denser parts
I/O Controller – Multiplexes data, command, and status word types. Decodes commands
Control Logic – Manages I/O transaction handshaking with Flash controller
Address Register – Identifies the block to be accessed for read or write
Data/Cache register – a single word static register to buffer data between I/O and Array
Status register – Flags errors in transactions and data flow
Row/Column Decode – breaks Address value into page values
Flash Array – the Flash cells arranged in rows and columns

Typical SSD Flash Component block diagram

The table below describes each of the I/O and Control lines in more detail for standard ONFI NAND Flash parts.

Control Line	Description	Usage
ALE	Input	Address latch enable: During the time ALE is HIGH, address information is transferred from I/O[7:0] into the on-chip address register. Upon a LOW to HIGH transition on WE#—when address information is not being loaded—the ALE signals should be driven LOW.
CE#	Input	Chip enable: Gates transfers between the host system and the NAND Flash device. After the device becomes busy or starts a PROGRAM or ERASE operation, CE# can be de-asserted. See “Bus Operation” on page 16 for additional operational details.
CLE	Input	Command latch enable: When CLE is HIGH, information is transferred from I/O [7:0] to the on-chip command register on the rising edge of WE#. When command information is not being loaded, the CLE signals should be driven LOW.
LOCK	Input	When LOCK is HIGH during power-up, the BLOCK LOCK function is enabled. To disable BLOCK LOCK, connect LOCK to VSS during power-up, or leave it unconnected (internal pull-down).
RE#	Input	Read enable: Gates transfers from the NAND Flash device to the host system.
WE#	Input	Write enable: Gates transfers from the host system to the NAND Flash device.
WP#	Input	Write protect: Protects against inadvertent PROGRAM and ERASE operations. All PROGRAM and ERASE operations are disabled when WP# is LOW.
I/O[7:0] (x8) I/O[15:0] (x16)	I/O	Data inputs/outputs: Bidirectional I/O signals transfer address, data and instruction information. Data is output only during READ operations; at other times the I/O signals are inputs.
R/B#	Output	Ready/busy: The ready/busy signal is an open-drain, active-LOW output, that uses an external pull-up resistor. The signal is used to indicate when the chip is processing a PROGRAM or ERASE operation. The signal is also used during READ operations to indicate when data is being transferred from the array into the serial data register. When these operations have completed, the ready/busy signal returns to the high impedance state.
VCC	Supply	VCC: The VCC ball is the power supply.
VSS	Supply	VSS: The VSS ball is the ground connection.

Some of the features of this standard include:

Discovery – allows the Flash controller to determine the characteristics of the Flash component
LUN addressing – allows the controller to activate operations on Flash components independently
Interleaving – allows the controller to synchronize operations on a set of Flash components
Caching – allows data to flow to/from controller independent of Flash array operations
Copyback – allows the Flash component to move data from one block to another without direct controller involvement

The key SSD Flash component suppliers on the market as of early 2010 include:

Hynix
Intel
Micron
SanDisk
Toshiba
Numonyx (ST Micro)
Samsung

Each supplier offers a variety of capacity, speeds, and features to set themselves apart from their competitors.

System designers perform a series of trade-offs when selecting a supplier and particular Flash component for their target SSD product and target market(s).

The trade-offs include:

Programmatic – cost, schedule, support, warranty, and availability.
Technical – performance, power, package options, features, scalability, and flexibility.
Other – commonality, compatibility, documentation, development support, testing, and reputation.

In the process of Flash component selection, the system designer is also doing the same analysis for the Flash controller and other parts needed in the SSD design. It is an iterative process to find the right combination of suppliers and components to best meet the requirements for the particular product.

Technology evolution

The next generation of Flash components are integrating more functionality into the basic component, and offering an intelligent interface rather than an ONFI type standard Flash memory bus used by SSDs today.

Initially this approach will allow NAND Flash components to be brought closer to the host processor bus for products such as mobile devices, offering large storage capacity and support for high definition data streaming and recording.

For the PC, there is currently no “DIMM” standard for NAND Flash in the PC. It’s needed. This would include a module size, connector, bus type, Error Management, and drivers.

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