XCENA showed two AI inference demonstrations built on its MX1 CXL computational memory at the OCP Global Summit 2026 in San Jose: a KV cache shared across inference servers through a CXL memory pool, and vector search for retrieval-augmented generation (RAG) run inside the memory device. SK hynix also unveiled a CXL Hybrid Memory product built on the MX1 chip at its booth, and the two companies are jointly optimizing RDMA-based shared-memory performance.
MX1 is a CXL 3.2 Type 3 memory device, which XCENA bills as the first CXL 3.2 computational memory, with a PCIe 6.0 dual x8 interface and support for up to 2TB of DRAM using 256GB DIMMs at two DIMMs per channel. Alongside memory expansion, the controller carries thousands of custom RISC-V cores with FP32 and FP16 vector engines for near-data processing, plus a separate PCIe 6.0 root complex that attaches SSDs for what XCENA calls InfiniteMemory.
Shared KV Cache and In-Memory Vector Search
In the first demonstration, multiple inference servers shared one KV cache held in a CXL memory pool. The KV cache stores context a model has already processed so it can be reused during generation, and keeping it in a shared pool removes the duplicate copies each server would otherwise hold, along with the data movement between servers. The approach parallels Samsung’s CMM-D pooling demo with AMD at the same show, and our KV 캐시 오프로드를 플래시에 적용 testing covers the flash tier below it.
The second demonstration used MX1’s near-data processing to accelerate vector search, a core step in RAG pipelines. MX1 runs the search inside the memory where the vector data resides, so large datasets do not have to move to the host processor on every query. XCENA has not published latency, throughput, or capacity figures for either demonstration or described the server configuration behind them.
SK hynix CXL Hybrid Memory Built on MX1
SK hynix’s CXL Hybrid Memory pairs DRAM with SSD capacity through InfiniteMemory, MX1’s SSD-backed memory expansion. The two companies say the architecture scales memory capacity well beyond conventional CMM-D DRAM modules while performing better than SSDs, and they are now validating it in real-world AI serving environments. At the summit, SK hynix showed the hybrid memory in an RDMA-based architecture, the shared-memory path the two companies are tuning together, following the CXL pooled memory work in its FMS 2026 demonstrations.
Sessions With Samsung, Marvell, Microsoft, Seagate, and Meta
XCENA Chief Product Officer Harry Kim presented “Bringing General-Purpose Parallel Programming to Near-Data Processing” on October 14 and joined Marvell, Samsung, SK hynix, and Gottbrath Technologies on a panel about open middleware for heterogeneous AI infrastructure. On October 15, he co-presented a session with Samsung Electronics on disaggregated CXL memory for agentic AI, covering dynamic pooling, sharing, and processing-near-memory offload. Distinguished Engineer Grant Mackey joined speakers from Microsoft, Seagate, and Meta the same day for the OCP Composable Memory Systems Sub-Project technical update on the memory wall.
“Improving AI infrastructure performance and efficiency is no longer solely a compute challenge. It also depends on how effectively memory is used and how much data movement can be eliminated,” said Jin Kim, CEO of XCENA. The company has raised $185 million to date, including a $135 million Series B, and is headquartered in Seongnam, South Korea, with a U.S. office in Sunnyvale, California.
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