Financial services infrastructure continues to be defined by the need to process larger risk models within fixed power and space constraints. As Monte Carlo-based analytics scale, system bottlenecks increasingly shift from compute to memory bandwidth, where data movement dominates runtime. Monte Carlo methods use repeated random sampling to calculate the probability of different outcomes in complex systems, quantifying risk across thousands of scenarios under high uncertainty.
A newly audited STAC-A2 benchmark result demonstrates the impact of pairing high-core-count processors with next-generation memory. An HPE ProLiant Compute XD230 1U server, configured with Intel Xeon 6980P processors and Micron 8800 MT/s DDR5 MRDIMMs, achieved the highest recorded performance for STAC-A2 cold runs at the baseline problem size, with tests run in HPE’s labs and independently audited by STAC on May 5, 2026. Results were generated using an Intel-optimized STAC-A2 implementation.
STAC-A2 as a Measure of Real-World Risk Workloads
STAC-A2 is widely used across capital markets to evaluate infrastructure performance for Monte Carlo simulation of option Greeks. These calculations underpin derivatives pricing, hedging strategies, and regulatory capital requirements. The benchmark reflects production-like workloads, emphasizing parallelism, memory bandwidth utilization, and latency sensitivity.
For trading firms and banks, incremental improvements in throughput or latency directly reduce end-of-day batch windows and enable more complex scenario analysis within existing operational timelines.
Record Performance and Generational Gains
In testing, the XD230 configuration delivered leading results across throughput, energy efficiency, and space efficiency among audited STAC-A2 submissions. Compared to a prior-generation platform using Intel Xeon Platinum 8592+ processors, the system demonstrated significant gains.
The STAC-A2 tests conducted by HPE in its labs achieved the highest throughput, energy efficiency, and space efficiency among all audited and tested STAC-A2 servers.
| Benchmark | Result | What It Measures |
|---|---|---|
| Portfolio Throughput | 100.8 options/sec | Options priced per second across a portfolio |
| Energy Efficiency | 231,271 options/kWh | Options priced per kilowatt-hour consumed |
| Space Efficiency | 133.8 options/hr/in cubed | Options priced per hour per cubic inch of server |
| Baseline Greeks (cold) | 0.033 seconds | Time to compute all Greeks, baseline problem size |
| Max Assets | 160 | Max assets completed in 10 min (25K paths, 252 timesteps) |
| Max Paths | 1,000,000 | Max paths completed in 10 min (5 assets, 252 timesteps) |
Portfolio throughput improved by 2.38x, while cold and warm runs of the baseline problem size were 10.42x and 1.62x faster, respectively. Large-problem-size runs saw improvements of 2.04x and 2.07x. Efficiency also improved, with 1.58x higher energy efficiency and 3.26x higher space efficiency.
These results indicate a substantial generational improvement, enabling higher compute density and faster time-to-insight without expanding infrastructure.
MRDIMMs Drive Memory Bandwidth Scaling
The system configuration included 24 x 64GB Micron DDR5 MRDIMMs operating at 8800 MT/s, providing up to 1.5TB of memory across 12 channels per socket. This memory subsystem is designed to meet the bandwidth demands of 256 total cores.
Monte Carlo workloads continuously move large datasets through memory during path generation, correlation, and regression steps. In this context, memory bandwidth directly affects both throughput and latency.
Compared to a similar Xeon 6980P configuration using RDIMMs, the MRDIMM-based system showed measurable gains. Portfolio throughput increased modestly from 93.2 to 100.8 options per second, while Greeks calculations improved by up to 23% on large problem sizes. Energy efficiency reached 231,271 options per kWh, up from 178,172, and space efficiency improved to 133.8 options per hour per cubic inch, up from 80.7.
These results reinforce that higher memory bandwidth can translate into tangible performance and efficiency improvements for data-intensive financial workloads.
Intel Xeon 6980P and Software Optimization
The Intel Xeon 6980P processor provides up to 128 performance cores per socket, along with 504MB of L3 cache and AVX-512 support for vectorized workloads. These features are aligned with the compute characteristics of Monte Carlo simulations.
The benchmark used the STAC-A2 Pack for oneAPI (Rev R) with the Intel oneAPI Base Toolkit and HPC Toolkit, version 2025.3. Intel has iterated on STAC-A2 implementations for over a decade, and this result reflects continued optimization at both the hardware and software levels.
Liquid Cooling Enables 1U Density
Achieving sustained performance from dual 128-core processors in a 1U chassis required liquid cooling. In this configuration, CPUs were connected to a coolant distribution unit (CDU) tied into the facility water loop, while other components remained air-cooled.
This hybrid approach enabled high compute density without thermal throttling. Compared to an air-cooled Xeon 6980P configuration, the liquid-cooled system delivered 1.23x better energy efficiency. It also achieved the highest reported efficiency for an Intel Xeon 6 system at 231,271 options per kWh, along with 65.8% better space efficiency than the next-best Xeon 6980P result.
Implications for Financial Data Centers
The benchmark highlights three areas of impact for financial institutions. Improved energy efficiency allows more calculations within fixed power budgets. Higher throughput reduces the time required for end-of-day and intraday risk runs. Increased density enables scaling within existing rack footprints.
These factors are particularly relevant for organizations operating under colocation constraints, power caps, or sustainability targets. The combination of MRDIMMs, high-core-count CPUs, and liquid-cooled 1U systems offers a path to expand analytics capacity without facility expansion.
Ecosystem Collaboration
The result reflects coordinated engineering across vendors. Intel provided the optimized STAC-A2 implementation, Micron supplied high-speed MRDIMMs to address bandwidth constraints, and HPE delivered the dense, liquid-cooled platform. STAC independently audited all results.
This submission builds on prior STAC-A2 work, where Micron memory helped deliver 35.2-millisecond results in an earlier collaboration. The current results extend those gains into throughput, efficiency, and density.
Full audited results are available from STAC under SUT ID INTC260430.
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