IBM introduced a new transistor architecture at the 0.7nm (7-angstrom) node, which it calls the industry’s first sub-1nm semiconductor technology. The development marks a significant research milestone as semiconductor manufacturers continue to push beyond the limits of traditional transistor scaling.
The experimental technology integrates nearly 100 billion transistors on a chip about the size of a fingernail, nearly doubling the transistor density of IBM’s 2nm chip technology first unveiled in 2021. According to IBM, the new design could deliver up to 50% higher performance or up to 70% greater energy efficiency compared to its 2nm node technology, depending on implementation targets.
At the center of the announcement is a new three-dimensional transistor architecture called “nanostack,” which IBM says enables logic scaling below the 1nm generation for the first time.
New 3D Nanostack Architecture
Rather than relying solely on conventional transistor shrinkage, IBM’s nanostack architecture vertically stacks and staggers nanosheet transistors through 3D sequential integration. This approach increases transistor density and allows different material combinations to be incorporated into individual layers, enabling independent optimization of performance and power characteristics within the stack.
IBM researchers reported successful experimental validation of the architecture through ultra-thin dielectric bonding for CMOS integration, demonstrations of dual-channel engineering, and the operation of functional CMOS inverter circuits. These results indicate that the architecture can be physically manufactured and support computational workloads.
Jay Gambetta, Director of IBM Research, characterized the development as a shift in chip construction methods rather than a simple transistor scaling exercise. He noted that the architecture enables operation at dimensions approaching atomic scales while delivering gains in both performance and efficiency.
SRAM Scaling for AI Workloads
In separate research presented at the 2026 Symposium on VLSI Technology and Circuits, IBM reported that the nanostack architecture achieved approximately 40% SRAM scaling. Memory density improvements are increasingly important for AI accelerators and high-performance computing systems, where bandwidth and memory capacity often limit overall system performance.
SRAM advancements could help designers build more efficient processors while meeting the growing memory demands of generative AI, cloud infrastructure, and data-intensive workloads.
Extending the Semiconductor Roadmap
Although modern process nodes no longer map directly to a specific physical transistor dimension, IBM’s 0.7nm technology demonstrates a potential path for continued logic scaling into the angstrom era. The company believes the nanostack approach could support at least another decade of transistor scaling beyond current leading-edge technologies.
The research was conducted at IBM’s semiconductor research center in Albany, New York, in collaboration with industry partners. The facility is expected to house a High Numerical Aperture Extreme Ultraviolet (High NA EUV) lithography system from ASML, a technology considered critical for future process generations. IBM and its partners have already reported working devices fabricated using High NA EUV processes.
Production Outlook
IBM continues to position itself as a leading semiconductor research organization, with contributions spanning silicon process technology, AI hardware, and quantum computing. The company recently announced plans to establish Anderon, a standalone quantum foundry focused on manufacturing quantum wafers.
While the 0.7nm technology remains a research achievement, IBM stated that the earliest commercial adoption of nanostack-based manufacturing could occur within the next five years, offering a potential path to production-class sub-1nm semiconductors.
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