AMD has announced the Kintex UltraScale+ Gen 2 FPGA family. They position the lineup as a mid-range refresh for bandwidth-hungry, latency-sensitive designs across medical, industrial automation, test and measurement, and professional broadcast. The company is emphasizing modernized memory and I/O, deterministic performance characteristics, and integrated security, along with long-lifecycle commitments that are common requirements for regulated, long-lived deployments.
Kintex UltraScale+ Gen 2 is framed as a step forward for teams that need more throughput and connectivity than prior mid-range platforms, but want to avoid moving into higher-cost device classes. AMD’s messaging centers on memory subsystem upgrades and I/O density as the primary levers for system-level gains, particularly for architectures that are bottlenecked by external memory bandwidth or constrained by PCIe lane and port density.
| XCKU3P | XCKU5P | XCKU9P | XCKU11P | XCKU13P | XCKU15P | XCKU19P | |
|---|---|---|---|---|---|---|---|
| System Logic Cells (K) | 356 | 475 | 600 | 653 | 747 | 1,143 | 1,843 |
| CLB LUTs (K) | 163 | 217 | 274 | 299 | 341 | 523 | 842 |
| DSP Slices | 1,368 | 1,824 | 2,520 | 2,928 | 3,528 | 1,968 | 1,080 |
| Memory (Mb) | 26.2 | 34.9 | 32.1 | 43.6 | 57.7 | 70.6 | 141.8 |
| GTH 16.3 Gb/s Transceivers | 0 | 0 | 28 | 32 | 28 | 44 | 0 |
| GTY 32.75 Gb/s Transceivers | 16 | 16 | 0 | 20 | 0 | 32 | 32 |
| I/O Pins | 304 | 304 | 304 | 512 | 304 | 668 | 540 |
AMD projects that the Kintex family can deliver up to 5x the memory bandwidth of the prior generation and up to 2x the channel density per PCIe interface. For OEMs and platform designers, those improvements typically translate into higher sustained throughput for streaming pipelines, faster buffering and capture, and tighter latency control for real-time analytics and control loops.
Targeting Data-Intensive Workloads in Key Vertical Markets
AMD is aligning the product with several specific workload profiles.
Broadcast and Production
In professional broadcast and remote production, the company highlights dense 4K and 8K workflows supported by high-speed transceivers and PCIe Gen4 connectivity. The target use cases include AV-over-IP transport, multi-stream capture, and frame-accurate signal movement, where deterministic behavior and sustained bandwidth are key to maintaining sync across complex pipelines.
Test and Measurement
In test and measurement and semiconductor inspection, AMD highlights increased memory bandwidth as a way to accelerate pattern generation, fault capture, and other timing-critical tasks. These platforms often operate under strict real-time constraints and are limited by how quickly data can be staged, captured, and processed near the interface.
Imaging and Robotics
For imaging and real-time control in machine vision, robotics, industrial automation, and medical imaging, AMD emphasizes scalable sensor connectivity and on-device processing. The intent is to support higher sensor counts and higher-resolution data streams while preserving responsiveness in feedback-controlled environments.
Memory and I/O Modernization
A notable architectural feature is the inclusion of integrated LPDDR4X/5/5X controllers, designed to deliver high DDR bandwidth with deterministic performance. AMD is targeting systems that must keep pace with rising data rates while managing latency and power efficiency. This challenge is particularly relevant in embedded and edge platforms where thermal and power budgets are fixed.
On connectivity, AMD is highlighting PCIe Gen4 support, and its performance projections reference configurations using PCIe Gen4x8 and hard Ethernet interfaces in competitive comparisons. As with most pre-launch claims, these are based on AMD engineering projections and published competitive specifications rather than field data.
Security and Long Lifecycle Support
AMD is also emphasizing security and longevity as differentiators in markets where supply assurance and certification stability matter. The company lists device-level security features, including authenticated operation, bitstream encryption, anti-cloning protections, secure key management, and CNSA 2.0-grade cryptography. For OEMs, these capabilities can reduce external security component requirements and simplify compliance efforts when the threat model includes IP theft, device cloning, or tampering in distributed deployments.
On lifecycle, AMD states planned availability through at least 2045. That is significant for medical, industrial, broadcast infrastructure, and test equipment programs where redesign cycles are expensive and recertification can be a multi-year process.
Development continuity is expected to remain anchored in AMD’s established toolchain, with the company citing ongoing support for Vivado and Vitis, as well as access to a mature portfolio of video, Ethernet, and connectivity IP.
Migration Path
AMD is offering a stated migration on-ramp via Spartan UltraScale+ devices. The company suggests teams can begin development with the XCSU200P in the SBVF900 package and plan to migrate to Kintex UltraScale+ Gen 2 in Q4 2026. This approach is designed for teams that want to start board and software bring-up earlier while aligning with the Gen 2 sampling window.
Availability
- Vivado and Vitis simulation support is scheduled for Q3 2026.
- Pre-production XC2KU050P silicon is expected to sample in Q4 2026.
- A Kintex UltraScale+ Gen 2 evaluation kit based on the XC2KU050, along with production silicon sampling, is also expected in Q4 2026.
- For earlier hands-on work with PCIe Gen4, hard controllers, and security features, AMD recommends the Spartan UltraScale+ SCU200 Evaluation Kit, based on the migration-capable XCSU200P.
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