Intel Panther Lake and Clearwater Forest processors are built on an 18A process node.
Intel detailed two next-generation platforms built on its U.S.-manufactured Intel 18A process node: the Intel Core Ultra Series 3 (code-named Panther Lake) client processor and Intel Xeon 6+ (code-named Clearwater Forest) for servers. Both products will be manufactured at Fab 52 in Chandler, Arizona, underscoring Intel’s strategy to anchor advanced process technology and packaging domestically for resilience and supply chain assurance.
Intel positions 18A as its first 2-nanometer-class node created and produced in the United States, combining RibbonFET transistors with PowerVia backside power delivery and Foveros advanced packaging. The promise is higher performance-per-watt, increased density, and scalable multi-chiplet architectures that translate into tangible gains for AI PCs, edge systems, and hyperscale data centers.
Intel CEO Lip-Bu Tan framed this as the start of a new era in computing driven by advances in process and packaging that will influence the coming decades. Summarizing his remarks: Intel’s next-generation compute platforms, built on cutting-edge process technology and advanced packaging, are intended to serve as engines of innovation while strengthening the company’s U.S.-based R&D, product design, and manufacturing footprint.
Panther Lake (Intel Core Ultra Series 3): Scalable AI PC Performance on 18A
Panther Lake is Intel’s first client SoC on 18A, built around a modular, multi-chiplet design to serve a wide range of consumer and commercial AI PCs, gaming devices, and edge systems. The platform targets a balance of high performance and mobile-class efficiency to fit premium thin-and-light notebooks and compact desktops while keeping thermals in check.
In terms of power and performance, Panther Lake is positioned to deliver Arrow Lake-class performance while operating with Lunar Lake-like power efficiency. Users can expect improved burst and sustained performance in common productivity, creation, and gaming tasks, all while maintaining battery life. For mobile form factors, this combination enables OEMs to design thinner systems with quieter cooling, while also maintaining headroom for on-device AI workloads.
The CPU complex scales up to 16 next-generation performance and efficient cores. Intel projects more than a 50% uplift in CPU performance versus the prior generation. This gain is attributable to a combination of architectural advances, process-driven improvements in frequency and power, and a more refined hybrid scheduling approach. This implies improved responsiveness across mixed workloads, better multi-thread throughput, and higher baseline performance under sustained load.
Greater Graphic Performance
Graphics is also getting a substantial lift. A new Intel Arc GPU with up to 12 Xe cores is targeting more than 50% higher graphics performance generation-over-generation. This directly benefits content creation, media encoding/decoding, and modern gaming at mainstream resolutions. For AI-centric workflows, the GPU improvements also translate into faster local inference for vision, media, and generative tasks that map well to GPU parallelism.
AI acceleration is a central design pillar. Panther Lake uses a balanced XPU approach, leveraging CPU, GPU, and NPU, to deliver up to 180 platform TOPS. That level of aggregate performance enables more AI models to run locally with lower latency and better energy efficiency. In enterprise deployments, this can reduce reliance on cloud inference for specific model types, improving privacy and responsiveness while lowering the operating costs of network egress and cloud compute.
Beyond traditional PCs, Panther Lake is designed to stretch into edge applications such as robotics. Intel is offering a Robotics AI software suite and a reference board that allow customers to combine deterministic control with AI perception on the same platform. For solution builders, this can shorten development cycles, consolidate bill of materials, and speed time-to-value for autonomous or semi-autonomous systems in manufacturing, logistics, and service robotics.
Availability-wise, Panther Lake is scheduled to enter high-volume production this year. Intel expects to ship the initial SKU before year-end, with complete market availability beginning in January 2026. OEMs and IT buyers planning refresh cycles can align pilot deployments late this year and broader rollouts as the supply ramps in early 2026.
Clearwater Forest (Intel Xeon 6+): E-core Density for Hyperscale and Cloud
Clearwater Forest, branded as Intel Xeon 6+, is Intel’s most power-efficient server CPU to date on the 18A node. It is designed around dense E-cores to maximize throughput and performance-per-watt for hyperscale, cloud service providers, and telcos where economics are dominated by core density, energy efficiency, and consolidation ratios.
At the core of Clearwater Forest is a substantial increase in core count—up to 288 E-cores—to address highly parallel, scale-out workloads. These include microservices, stateless web services, content delivery, stream processing, telco network functions, and AI inference scenarios where high thread counts and efficient scheduling drive aggregate throughput. The design focus is to deliver more useful work per rack unit while staying within tight power and cooling envelopes.
Architecturally, Clearwater Forest targets a 17% uplift in instructions per cycle over the prior generation. This indicates real microarchitectural improvements beyond simply adding more cores. For operators, the combination of higher IPC and greater core density should reduce energy per transaction and increase container density, leading to fewer racks for equivalent workload capacity and improved total cost of ownership.
From an efficiency and density standpoint, Clearwater Forest aims to provide considerable gains in rack-level performance and power usage effectiveness. In modern containerized and orchestrated environments, this translates into better utilization, fewer stranded resources, and improved service consolidation. The platform is well-suited to environments that prioritize predictable scaling and low operating costs across massive fleets.
Intel plans to launch Xeon 6+ in the first half of 2026. For capacity planners and procurement teams, this timeline supports modeling for mid-2026 deployments and phased migrations for services that benefit most from E-core consolidation economics.
Intel 18A: U.S.-Built, Next-Gen Transistor and Power Delivery
Intel 18A is positioned as the first 2-nanometer-class node developed and produced in the United States. Relative to Intel 3, 18A targets up to 15% better performance per watt and 30% higher density. Development, qualification, and initial production took place in Oregon, with Arizona now ramping up high-volume manufacturing.
The node introduces several foundational technologies. RibbonFET, Intel’s first new transistor architecture in over a decade, adopts a gate-all-around approach to improve scaling and switching efficiency. The expected outcome is higher performance at lower power, enabling more aggressive performance targets within given thermal budgets. PowerVia, a backside power-delivery system, separates power and signal layers to reduce IR drop and improve signal integrity. This design can support higher frequencies and better energy efficiency by delivering cleaner power to transistors. Complementing these is Foveros’ advanced packaging, which enables 3D chip stacking and heterogeneous chiplet integration. Foveros enables Intel to compose SoCs from multiple dies tailored to specific roles, improving yields and giving product teams greater flexibility to optimize for cost, performance, and thermals across market segments.
Strategically, Intel 18A forms the foundation for at least three upcoming client and server generations. For enterprise and cloud buyers, that translates into roadmap continuity and compounding benefits as design teams iterate on the same set of transistor, power delivery, and packaging capabilities.
Fab 52: Domestic Scale for Leading-Edge Logic
Fab 52 at Intel’s Ocotillo campus in Chandler, Arizona, is the company’s fifth high-volume fab at the site and manufactures what Intel describes as the most advanced logic chips produced in the United States. It is part of Intel’s broader $100 billion investment to expand domestic operations. Together with cutting-edge R&D, initial production in Oregon, and advanced packaging capabilities in New Mexico, Fab 52 anchors an end-to-end, U.S.-based design and manufacturing pipeline.
For customers, this footprint is relevant for resilience and compliance. A domestically anchored supply chain reduces exposure to overseas logistics and geopolitical risks at advanced nodes. It also supports requirements for trusted manufacturing in sensitive government and regulated industry deployments. With AI demand accelerating, Fab 52 provides the scale to support both Intel’s own platforms and Intel Foundry clients seeking leading-edge capacity in the U.S.
Perspective for Technical Sales and Procurement
For client fleets, Panther Lake’s combination of more than 50% CPU and graphics uplift, and up to 180 platform TOPS positions it as a strong catalyst for AI PC refresh cycles. Organizations aiming to move inference to the edge can expect lower latency and improved privacy while potentially reducing cloud compute and egress costs for appropriate workloads. The multi-chiplet flexibility should give OEMs and channel partners finer-grained SKU differentiation to match vertical and workload-specific needs.
In the data center, Clearwater Forest’s E-core density and 17% IPC improvement are designed to reduce energy per request and increase container density. The outcome is improved rack utilization and a path to consolidating services without compromising throughput. This is an attractive lever for hyperscalers, SaaS providers, and telcos managing power-constrained facilities.
Panther Lake is slated to enter high-volume production this year, with initial SKUs shipping before year-end and broad market availability targeted for January 2026. Clearwater Forest is planned for the first half of 2026.
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