AMD announced that its upcoming Versal adaptive SoCs will natively support Universal Chiplet Interconnect Express (UCIe) 1.1 interfaces. The open industry standard, which Intel is also building into Diamond Rapids and Wildcat Lake, establishes low-power, high-bandwidth die-to-die communication, allowing co-packaged AMD adaptive SoCs to interface directly with specialized silicon. This transition targets the engineering constraints of traditional monolithic SoCs by enabling modular, multi-die architectures that compress development timelines, reduce non-recurring engineering costs, and optimize package-level power and latency.
The initial rollout will center on the AMD Versal RF Series, making them the first adaptive SoCs in the portfolio to feature native UCIe 1.1 connectivity. The architecture will accommodate up to four independent UCIe Standard Package (UCIe-SP) interfaces and up to two UCIe Advanced Package (UCIe-AP) interfaces, with AMD listing the x16 UCIe-SP links at up to 16 GT/s and the x64/x32 UCIe-AP links at up to 8 GT/s, yielding multi-terabit-per-second aggregate in-package bandwidth. As enterprise and embedded system requirements evolve, AMD plans to expand UCIe support across additional adaptive SoC families, following the in-package integration path it started with the Versal Premium Gen 2 memory-on-package part families.
Versal RF Series devices consolidate high-resolution RF data converters, dedicated hard IP for DSP, AI Engines, and programmable logic into a unified package. The platform provides up to 80 TOPS of heterogeneous DSP compute while delivering notable size, weight, power, and cost (SWAP-C) optimizations by consolidating the functional footprint of multiple discrete ICs.
Replacing Board-Level Links With In-Package Chiplets
Native UCIe integration eliminates the need to route high-speed signals across printed circuit boards, replacing legacy board-level serialized interfaces, such as GTM transceivers, with standardized in-package interconnects. This allows hardware engineers to tightly couple Versal RF silicon with specialized companion chiplets, including third-party RF analog front ends (AFEs), dedicated AI accelerators, host CPUs, specialized GPU compute blocks, custom hardware security modules, communications processors, co-packaged optics (CPO), and application-specific ASICs.
By facilitating direct interoperability between multi-vendor and custom silicon, UCIe support reduces interconnect latency, minimizes overall power draw, and provides system architects with the flexibility to reuse proven silicon IP. Production chiplets featuring UCIe 1.1 connectivity are scheduled to become available on select Versal RF Series devices in the fourth quarter of 2027.
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