Synopsys has announced what it describes as the industry’s first complete Compute Express Link (CXL) 4.0 intellectual property suite. The portfolio combines a CXL controller, IDE security modules, a PCIe 7.0-based physical layer, and verification IP for system-on-chip designers building AI infrastructure. The verification piece has been shipping since December 2025, when Synopsys called it the first commercially available CXL 4.0 verification IP; the controller, security modules, and PHY are what complete the set.
The announcement shows a broader shift in AI system design. As model sizes and context windows expand, memory capacity, bandwidth, and access latency increasingly limit performance. Large language model inference depends on moving model weights, key-value caches, and shared state between processors, accelerators, and memory. Goldman Sachs Research estimates global AI token consumption could increase 24 times by 2030, reaching about 120 quadrillion tokens per month.
CXL is designed to address these requirements through a cache-coherent interconnect operating over the PCI Express physical layer. The standard enables CPUs, XPUs, accelerators, and memory devices to share resources while supporting memory expansion, pooling, and fabric-based architectures.
CXL 4.0 Doubles Bandwidth
CXL 4.0 increases link speed to 128 GT/s, equaling the bandwidth of PCIe 7.0. Synopsys states that the new specification maintains the latency characteristics of CXL 3.x while doubling available system bandwidth.
The specification also adds bundled port capabilities. Four x16 links provide more than 2 TB/s of aggregate bandwidth, while eight x16 links exceed 4 TB/s. CXL 4.0 supports up to four retimers and native x2 link widths, extending connectivity options for rack-scale systems. The other significant addition in the 2025 specification is on the reliability side, with memory RAS enhancements covering granular event reporting, Post Package Repair, and flexible memory sparing.
These capabilities support disaggregated compute and memory architectures. Synopsys claims CXL-based key-value cache offload delivers three to six times the performance of SSD-based alternatives at 128 GT/s. The company also cites CXL.mem load-to-use latency below 200 nanoseconds and rack-scale memory pools exceeding 100 TB. According to Synopsys, these capabilities could reduce inference costs by 50% to 100%, depending on system configuration and workload.
Design Challenges Extend Beyond the Controller
Implementing CXL 4.0 requires more than adding a new controller to an SoC. AI system designers must support multiple CXL generations and manage differences in memory capacity, bandwidth, availability, and system topology. CXL 4.0 maintains backward compatibility with earlier versions, allowing new designs to use existing infrastructure while migrating to higher-speed fabrics.
Security is another consideration. Cloud and multi-tenant AI deployments require authenticated and encrypted coherent memory access anchored to a hardware root of trust. Synopsys says its IDE implementation provides that protection without adding cycle-level latency in CXL.cache and CXL.mem skid modes.
The AI infrastructure market also pressures development schedules. System designers must typically accommodate rapidly changing accelerator architectures and hyperscale deployment requirements. Delays in verification, interoperability testing, or physical-layer qualification can therefore affect the entire SoC schedule.
Synopsys CXL 4.0 IP Portfolio
The Synopsys CXL controller supports CXL 4.0 at 128 GT/s, along with CXL 3.x, 2.0, and 1.x. It includes bundled ports, port-based routing, and a 256-byte FLIT mode to reduce latency. The company says a single license covers the supported CXL generations and includes PCIe 7.0 fallback without requiring a separate PCIe 7.0 IP license.
The IDE security modules use AES-GCM encryption and authentication and support TSP and TDISP features for confidential computing. Synopsys also states that the implementation is designed for FIPS 140-3 certification readiness.
The CXL physical layer is based on a silicon-proven PCIe 7.0 SerDes operating at 128 GT/s. Synopsys says the PHY is hardened for process nodes from 5nm to 2nm and includes low-jitter tolerance and low-latency forward error correction.
The verification IP is the oldest piece of the stack. Synopsys introduced it in December 2025 as the industry’s first commercially available CXL 4.0 VIP, supporting the full 128 GT/s data rate along with IO throttling and streamlined port negotiation, and offering migration paths from CXL 3.0 and PCIe 7.0. The verification environment is intended to support compliance and interoperability testing before tape-out, reducing the risk that standards validation becomes a late-stage development bottleneck.
Synopsys positions the unified architecture to support CXL migration across multiple product generations. The company cites more than 25 years of PCIe development, over 3,800 PCIe design wins, and more than 170 CXL controllers and PHYs shipped. It has taken a similar portfolio approach to other AI fabrics, including the Ultra Ethernet and UALink IP it introduced for accelerator clusters.
Part of a Broader HPC IP Portfolio
The CXL 4.0 offering is part of Synopsys’ broader high-performance computing IP portfolio. The portfolio includes interface IP for CXL, PCIe, UCIe, UALink, Ultra Ethernet, ESUN, and high-speed Ethernet PHYs supporting 224G and 448G links.
It also includes foundation IP such as memory, logic libraries, and standard cells for advanced process nodes. Security components cover hardware roots of trust, physically unclonable functions, post-quantum cryptography, security accelerators, and interface protections, including PCIe and CXL IDE, IME, MACsec, and UALinkSec.
Synopsys also offers pre-integrated IP subsystems intended to reduce the amount of integration and verification required for XPU, accelerator, and hyperscaler SoC designs. Together, these components target the interconnect, memory, security, and compute requirements of rack-scale AI infrastructure.
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